1. Field of Invention
Embodiments of the invention relate in general to integrated circuits. More specifically, the embodiments of the invention relate to the methods and systems for improving communication between logic elements in an integrated circuit.
2. Description of the Background Art
Integrated circuits (ICs) are typically designed by using automated placement and routing of functional cells (standard cells). Currently, an automated IC physical design involves various stages of placing functional cells on a layout. This is followed by routing wires between the cells and optimization of the cells and wires in the physical design.
Further, the advancement in semiconductor technology makes the physical design process increasingly complex. Thus, it becomes difficult for the methodology and computing hardware to deal with the increasing size of physical designs. A Deep Sub-Micron (DSM) process technology demands more in-depth analysis, in order to deal with increasing assortments of physical effects that impact the design performance or reliability. In-depth analysis involves increasing the types of analysis, number of conditions, resolution of the analysis, etc. Thus, DSM physical design algorithms need to be highly complex in order to address a wide variety of circuit topologies coupled with DSM physical effects.
Specifically, the operating behavior of many DSM application-specific ICs (ASICs) is primarily being determined by the characteristics of the wires, rather than the performance of the gates. The most computational-intensive analysis and optimization steps being performed during a DSM physical design are concentrated on the wires. The conventional techniques for physical design are, however, gate-oriented, even though the physical design issues are predominantly wire-oriented.
The methods and systems for approaching IC placement and routing, to address the increase in complexity in terms of design size and/or DSM physical effects, are known in the art. However, conventional methods do not permit easy layout and analysis. The methods do not focus on, and facilitate implementation of the wires. The existing methods do not enable simplified physical topologies, and decoupling of DSM physical effects. Therefore, the above-mentioned limitations of the conventional designing process may result in impaired communication between the logic cells. Impaired communication between the logic cells hinders timing and power optimization, as well as other operational characteristics of the physical design.